Dr Bruce Sham
M. Phil., Ph. D., IEEE SM.
I received a Bachelor degree (Computer Engineering) and an MPhil. degree from the Chinese University of Hong Kong in 2000 and 2002 respectively, and received the Ph.D. degree from the same university in 2006. I began my research work on digital design during the final year project as an undergraduate which focused on improving the performance, reducing the logic complexity of the system and, hence, power consumption. I have worked as an Electronic Engineer on the FPGA applications of the motion-control system and system security with cryptography in ASM Pacific Technology Ltd (HK). During the years at the Hong Kong Polytechnic University, I have also engaged in various University projects for the commercialization of technology, in particular, a few optical communication projects which are in collaboration with Huawei. I also worked on the physical design of VLSI design automation. I was invited to work at Synopsys, Inc (Shanghai) in the summer of 2005 as a Visiting Research Engineer. I also obtained the Best Paper Award in ISQED 2013 and the Best Paper Award in ATC 2015. I am now an IEEE Senior Member and is working at The University of Auckland as Senior Lecturer.
Research | Current
Hardware Acceleration (using FPGA) of Digital Systems includes: Genomic Analysis, Neural Network and Telecommunication
Software Development on Physical design of VLSI includes: Floorplanning, Placement, Routing, Clock planning and Power management
Current PhD students:
Studying at The University of Auckland (PhD)
-Lo, ChunYan (enrolled in July 2019)
-Ma, Longyu Sean (enrolled in Feb 2018)
-Valencia, Raul (enrolled in Nov 2017)
Studying at The Hong Kong Polytechnic University (PhD, Co-supervisor)
- Jiang, Sheng (enrolled in 2015)
- Zhang, Pangwei (enrolled in 2016)
Areas of expertise
- Digital Design with FPGA
- Design Automation of VLSI
Associate Editor of IEEE Transactions on Circuits and Systems II
Selected publications and creative works (Research Outputs)
- Ma, L., & Sham, C. W. (2020). Iris Recognition System Implementation Improved by QC-LDPC codes. LifeTech 2020 - 2020 IEEE 2nd Global Conference on Life Sciences and Technologies. 10.1109/LifeTech48969.2020.1570619090
- Tenorio, R. H. V., Sham, C.-W., & Vargas, D. V. (2020). Preliminary study of applied binary neural networks for neural cryptography.. GECCO Companion.
- Zhang, P. W., Lau, F. C. M., & Sham, C.-W. (2020). Protograph-based LDPC-Hadamard Codes.. WCNC.
- Valencia, R., Sham, C. W., & Sinnen, O. (2019). Evolved binary neural networks through harnessing FPGA capabilities. Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019. 10.1109/ICFPT47387.2019.00076
Other University of Auckland co-authors: Oliver Sinnen
- Xu, Z., Wang, L., Hong, S., Lau, F. C. M., & Sham, C.-W. (2019). Joint Shuffled Scheduling Decoding Algorithm for DP-LDPC Codes-Based JSCC Systems. IEEE WIRELESS COMMUNICATIONS LETTERS, 8 (6), 1696-1699. 10.1109/LWC.2019.2937766
- Jiang, S., Zhang, P. W., Lau, F. C. M., Sham, C. W., & Huang, K. (2019). A Turbo-Hadamard Encoder/Decoder System with Hundreds of Mbps Throughput. International Symposium on Turbo Codes and Iterative Information Processing, ISTC. 10.1109/ISTC.2018.8625371
- Chou, H.-F., & Sham, C.-W. (2018). An Optimization Approach for an RLL-Constrained LDPC Coded Recording System Using Deliberate Flipping. IEEE COMMUNICATIONS LETTERS, 22 (10), 1976-1979. 10.1109/LCOMM.2018.2863363
- Zhou, H., Sham, C.-W., & Yao, H. (2018). Revisiting routability-driven placement for analog and mixed-signal circuits. ACM Transactions on Design Automation of Electronic Systems, 23 (2)10.1145/3131849